Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. The volatile memory devices lose their stored data when their power supplies are interrupted, however non-volatile memory devices retain their stored data even when their power supplies are interrupted. Thus, non-volatile memory devices are widely used in memory cards, mobile telecommunication systems and other devices that are susceptible to power interruption.
Non-volatile memory devices typically employ flash memory cells having stacked gate structures. Each of the stacked gate structures comprises a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked on a channel region of a transistor. To enhance reliability and program efficiency of the flash memory cell, the film quality of the tunnel oxide layer can be improved and a coupling ratio of the cell can be increased. Recently, a phase change memory cell has been proposed as an alternative to the flash memory cell.
FIG. 1 is a cross sectional view showing a data storage element that is employed in a conventional phase change memory cell. Other conventional memory devices that utilize phase-change materials are disclosed in U.S. Pat. No. 6,507,061. Referring to FIG. 1, a lower interlayer insulation layer 3 is disposed on a semiconductor substrate 1. A predetermined region of the semiconductor substrate 1 is exposed by a contact hole 5a that passes through the lower interlayer insulation layer 3. The contact hole 5a generally has a positive sloped sidewall. In other words, an upper diameter of the contact hole 5a is greater than a lower diameter thereof. In particular, the higher the aspect ratio of the contact hole 5a, the greater the narrowing of the contact hole 5a. This is due to a characteristic of dry etch processes that are typically used in the formation of the contact hole 5a. Accordingly, if the thickness of the lower interlayer insulation layer 3 is increased, the substrate 1 may not be exposed even though the dry etch process for forming the contact hole 5a is performed for a long duration. The contact hole 5a is filled with a conductive plug 5b. A void 5c or seam may be formed inside the conductive plug 5b. The void 5c or seam is generated during formation of the conductive plug 5b. In the event that the aspect ratio of the contact hole 5a is high, the void 5c or seam can be easily formed.
A phase change material layer pattern 7 and a top electrode 9 are sequentially stacked on the substrate having the conductive plug 5b. The phase change material layer pattern 7 covers the conductive plug 5b. The phase change material layer pattern 7 is typically formed of a material that exhibits two stable states according to temperature. For example, the phase change material layer pattern 7 may be formed of a GeSbTe layer (hereinafter, referred to as a GST layer). In more detail, if the GST layer is heated to a temperature higher than the melting point and cooled down rapidly, the GST layer will have an amorphous state, which is a relatively high resistance state. On the contrary, if the GST layer is heated to a temperature between the melting point and a crystallization temperature and cooled down, the GST layer will have a crystalline state, which is a lower resistance state. Thus, the GST layer operates as a programmable resistor, having high and low resistance states that determine whether the memory cell is storing a logic 0 or a logic 1 value. The GST layer can be heated by current that flows through the GST layer. It may be advantageous to decrease the contact area between a conductive plug 5b and the phase change material layer pattern 7 in order to reduce the power that is needed for phase transition of the GST layer. In other words, it is preferable that the upper diameter of the contact hole 5a be decreased. However, if the upper diameter of the contact hole 5a is reduced, the semiconductor substrate 1 may not be exposed. This is because the sidewall of the contact hole 5a has a positive slope as mentioned in the foregoing description.
The GST layer can react with a conductive layer such as a doped polysilicon layer. When the GST layer reacts with the polysilicon layer, silicon atoms in the polysilicon layer migrate into the GST layer and increase the resistance of the GST layer. When this occurs, it becomes more difficult to use the GST layer as a phase change material layer. To address this problem, the conductive plug 5b and the top electrode 9, which are in direct contact with the phase change material layer pattern 7, are typically formed of a stable material layer that does not react with the phase change material layer pattern 7. For instance, a metal nitride layer, such as a titanium nitride layer, is widely used in formation of the conductive plug 5b and the top electrode 9. The lower interlayer insulation layer 3, which surrounds the phase change material layer pattern 7, is covered with an upper interlayer insulation layer 11. A plate electrode 13 is disposed on the upper interlayer insulation layer 11, and the plate electrode 13 is electrically connected to the top electrode 9.
As described hereinabove, voids or seams can be formed in the conductive plugs 5b. Therefore, the phase-change material may fill the voids or the seams during fabrication. To prevent this, the contact area between the phase-change material layer pattern and the conductive plug is typically increased, but this increase in contact area can degrade the operating characteristic of the phase-change memory cell by increasing the power required during a writing operation.